1 GB DDR 333 SO Dimm
DLL aligns DQ and DQS transition with CK transition
Double-data-rate architecture
Bi-directional data strobe (DQS)
Differential clock inputs (CK and /CK)
Auto refresh and self refresh
8192 refresh cycles / 64ms
Power supply: Vdd,Vddq:2.5V�0.1V
Programmable Burst length (2,4,8)
Serial Presence Detect with EEPROM
Double-data-rate architecture
Bi-directional data strobe (DQS)
Differential clock inputs (CK and /CK)
Auto refresh and self refresh
8192 refresh cycles / 64ms
Power supply: Vdd,Vddq:2.5V�0.1V
Programmable Burst length (2,4,8)
Serial Presence Detect with EEPROM
Your post really cool and interesting. Thanks very much.
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